The present invention relates to multi-collector transistor structures and, more particularly, to a merged multi-collector transistor structure for providing a plurality of predetermined weighted output currents.
There are a myriad of applications for current source schemes for providing multiple related output current sourcing. For example, digital-to-analog converters (DACs) require the generation of a plurality of binary weighted output currents to convert a digital input signal to an analog output signal as is well understood. Most DACs today require a R-2R ladder network to produce the binary weighted output currents.
A problem with using R-2R ladder networks is that the physical size thereof takes up a significant portion of the DAC chip area if the DAC is fabricated in integrated circuit form. R-2R ladders also require voltages and switches that do not lend themselves easily to single five volt systmes. In today's environment it is desired to provide more and more complex circuitry on single integrated circuit chips while reducing the cost thereof as well as increasing yields. The need for a R-2R ladder network for multiple bit DAC's can limit the complexity of the integrated circuit that can be realized due to this physical limitation.
Moreover, the resistors of the R-2R ladder network must be matched to close tolerances to ensure good accuracy of the DAC. These tolerances must be maintained during fabrication of the integrated circuit. Further, the resistors must track with temperature variations.
In view of the drawbacks related with using R-2R ladders, it is desirable to provide a means for producing multi-weighted output currents which require minimum spacing while providing minimum current ratio errors. Thus, there is a need for a current source for producing multiple related output currents therefrom.